Happy new year everyone! Today we're releasing Spade 0.12.0. All in all, this is quite a boring release (in a good way) that mostly fixes a ton of bugs, but there are some new features too.

Swim changes🔗

The build tool has seen quite a few nice improvements in this release

Gowin support🔗

Gowin FPGAs are now supported by swim which makes using Spade on one as simple as

swim init --board tangnano9k

If you have one of these FPGAs lying around, now is a great time to try Spade!

Less Chatty Swim Output🔗

Swim will now only print output from commands that fail or those that end up running for more than a few seconds. This makes it easier to filter out the unimportant parts of the log, and it looks a bit cleaner. You can see it in action here: [https://asciinema.org/a/j9HRvwzAWnoFBVCt4Zj8wM2LE]

Other Swim changes🔗

If you use swim install-tools we now use a bleeding edge oss-cad-suite again. Beyond enabling the gowin support, this should give a nice improvement in performance thanks to improvements in yosys and nextpnr that we've been missing out on due to the pinned cad suite.

Methods on Arrays and Wires🔗

You can now add methods to arrays and wires. This is of course useful in user code, and also allows us to add some missing conversion functions to the standard library.

You can now use .to_int() and .to_uint() on arrays of bools ([bool; N]), where you previously had to use bits_to_int() and bits_to_uint()

Bug Squashing🔗

We've fixed quite a few bugs with this release. A lot of them related to compiler panics or miscompilations when writing zero size types.

• Fix a few codegen bugs around enums with 1 variant and no members
• Fix codegen bug when matching on zero size literals
• Fix codegen bug when using zero size integers

Beyond fixing these specific cases, we've made the handling of zero size types much more robust to errors since that has been a source of nasty bugs.

We fixed another nasty codegen bug that has been around for a while when indexing nested inverted wire structures

We also fixed a few errors with patterns

• Report error when integer patterns are out of bounds
• Fix panic when pattern matching arrays of integers with more than 4 elements

Verilog annoyingly requires special handing for arrays of single bit values. This was missing from the code generator for memories which prevented the synthesis tool from inferring memories for clocked_memory<bool>. This has now been fixed

Nearly all of these bugs were reported by users, so thanks to everyone that has been trying out the language and reporting issues!

Parser tweaks🔗

Finally, we made some small but important tweaks to the parser

You no longer need to have a new line at the end of a line comment at the end of a file

The compiler no longer allows non-block expressions in if branches.

And finally, we adjusted the precedence of the dereference (*) and bitwise operators to make more sense and require fewer parenthesis.